The invention relates generally to the field of circuit design, and in particular to an improved multi-port memory cell.
In super-scalar, Very Long Instruction Word (VLIW) processors and in network processors, memory cells with multiple write ports are typically required. These multiple write ports are associated with multiple bit lines that allow both writing the same data to many memory cells as well as allowing direct communication paths from the multiple execution units to one memory cell.
Prior art multi-port register memory cells used a single write word line for each differential write bit line or a differential write word line for each single write bit line. Using differential word or bit lines caused a large line count which in turn increased the layout area for the memory cell.
FIG. 1 is an example of another prior art multi-write port memory cell. FIG. 1 was a first step in reducing the layout area over the above differential word or bit line memory cell. For illustration purposes, only the write ports are shown. FIG. 1 shows only one memory cell in an array of memory cells in a multi-port register file. The memory cell has back-to-back inverters 156 and 158, which have nodes 152 and 154. There are six word lines (WLs), i.e., WLA, WLB, WLC, WLD, WLE, and WLF, and six write ports shown by six data bit lines (BLs), i.e., BLA, BLB, BLC, BLD, BLE, and BLF. There is a one-to-one correspondence between a write word line and a write bit line (i.e., a write port). For example, word line WLA has transistor 112 which is a switch to allow a connection of bit line BLA to node 152. Word line WLA also is connected to transistor 114, which is a switch to allow a connection to ground of node 154 through transistor 140, when bit line BLA is xe2x80x981xe2x80x99. The one-to-one correspondence holds also for WLB and BLB, WLC and BLC, WLD and BLD, WLE and BLE, and WLF and BLF.
An example of the operation of the circuit 110 in FIG. 1 is when word line WLA is xe2x80x981xe2x80x99. Transistors 112 and 114 are turned on. Subsequently, if bit line BLA is xe2x80x981xe2x80x99, transistor 140 is turned on and pulls node 154 down to ground gnd. The bit line BLA value of xe2x80x981xe2x80x99 goes through transistor 112 to node 152. Back-to-back inverters 156 and 158 will maintain node 152 at xe2x80x981xe2x80x99 and node 154 at xe2x80x980xe2x80x99. Similarly, for example, when word line WLD is xe2x80x981xe2x80x99, transistors 122 and 124 are turned on. If bit line BLD is xe2x80x981xe2x80x99, then transistor 146 is turned on pulling node 154 to ground gnd. Node 152 has the value of bit line BLD. If bit line BLD is xe2x80x980xe2x80x99 then transistor 146 is off. Node 152 is pulled to xe2x80x980xe2x80x99 and node 154 is pulled to xe2x80x981xe2x80x99 by inverter 156.
A conventional final decoding circuit of the prior art, applicable to FIG. 1, is shown in FIG. 2. This example assumes that addresses for write ports A through F, i.e., word lines WLA to WLF of FIG. 1, have been pre-decoded, such that the final decode consists of a 2-input AND gate, implemented here using a dynamic circuit. For instance the AND gate of port A includes a transistor 214 with address input A0 and a transistor 216 with an address input A1. The signal pc is a precharge signal, usually a clock signal. When pc=xe2x80x980xe2x80x99, node 213 is xe2x80x9cprechargedxe2x80x9d to a xe2x80x981xe2x80x99 via transistor 212. An AND gate, i.e., transistor 214 connected in series to transistor 216, is disabled because transistor 218 is turned off. The address A0 and A1 is then read when pc=xe2x80x981xe2x80x99. Transistor 218 is turned on, hence enabling the AND gate, i.e., transistors 214 and 216. Node 213 is pulled to ground when both A0 and A1 are xe2x80x981xe2x80x99, otherwise node 213 remains xe2x80x981xe2x80x99. When node 213 is xe2x80x980xe2x80x99, WLA is xe2x80x981xe2x80x99 via inverter 270. The other five AND gates having address lines B0, B1 to F0, F1 operate in a similar manner as the AND gate for A0, A1. The outputs of decoder circuit 210 are word lines WLA to WLF which is then input into word lines WLA to WLF of FIG. 1.
While the circuit of FIG. 1 gives a reduced area compared to its predecessors, there is still need for improvement, because there is a continuing demand for more memory in a smaller area. Thus a new circuit is needed which uses less area than the prior art.
The present invention provides an improved multi-port memory cell circuit which has fewer write lines than conventional multi-port memory cells, and hence occupies a smaller area. In addition, according to the preferred embodiment, there are fewer transistors than FIG. 1. Power consumption may also be reduced.
One embodiment of the present invention comprises a method for reducing an area of a memory cell circuit, where the memory cell includes a first plurality of bit lines and a plurality of word lines associated with each bit line. First, a first word line is used for selecting a second plurality of bit lines from the first plurality of bit lines. Next a second word line is used for selecting a bit line of the second plurality of bit lines. And then, a bit value on the bit line is stored in a memory cell.
An aspect of the present invention includes a reduced area memory cell circuit comprising: a plurality of word lines associated with each bit line of a first plurality of bit lines; a first word line of the plurality of word lines for selecting a second plurality of bit lines from the first plurality of bit lines; a second word line of the plurality of word lines for selecting a bit line of the second plurality of bit lines; and a memory cell for storing a bit value on said bit line.
Another embodiment of the present invention comprises a memory cell circuit comprising: a memory cell for storing data; a first word line and a second word line; a plurality of bit lines; a first switch controlled by the first word line, where the first switch connects a first bit line of said plurality of bit lines to a first node; and a second switch controlled by the second word line, where the second switch connects the first node to the memory cell.
Yet another embodiment of the present invention comprises a system for writing data to a memory cell. The system comprises: a first multiplexer for selecting a first bit line of a plurality of bit lines, when a first word line selects the first bit line; a second multiplexer for selecting a second bit line of the plurality of bit lines, when the first word line selects the second bit line; and a third multiplexer for selecting between an output of the first multiplexer and an output of the second multiplexer based on a second word line, wherein an output of the third multiplexer writes data to the memory cell.
A further embodiment of the present invention comprises a system for providing a plurality of selector signals to a first multiplexer and a second multiplexer, wherein the first multiplexer receives data from a bit line having a bit line address, and wherein the second multiplexer receives data from the first multiplexer and writes the data to a memory cell. The system comprises: a first plurality of decoders for receiving a first plurality of bit line addresses and producing a first plurality of write enable signals; at least one logic gate for combining the first plurality of write enable signals into a first selector signal of the plurality of selector signals, where the first selector signal controls the first multiplexer; a second plurality of decoders for receiving a second plurality of bit line addresses and producing a second plurality of write enable signals; and at least one logic gate for combining a write enable signal of the first plurality of write enable signals and a write enable signal of the second plurality of write enable signals into a second selector signal of the plurality of selector signals, where the second selector signal controls the second multiplexer.
Another aspect of the present invention provides a memory cell circuit having a first plurality of bit lines. The memory cell circuit includes: means for selecting a second plurality of bit lines from the first plurality of bit lines; means for selecting a bit line of the second plurality of bit lines; and means for writing a bit value on the bit line to a memory cell.
These and other embodiments, features, aspects and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings.